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L5951
TRIPLE OUTPUT MULTIFUNCTION VOLTAGE REGULATOR FOR CAR RADIO WITH IDR/CLASS 2 INTERFACE
s
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3 VOLTAGE REGULATORS: 3.3V (100mA) STANDBY REGULATOR 5V (100mA) STANDBY REGULATOR 7.8V (100mA) OUT OF REGULATION DETECTION FOR 5VSTANDBY REGULATOR WIDE OPERATING SUPPLY VOLTAGE RANGE FROM 4.5V UP TO 26.5V FOR TRANSIENT 34V VERY LOW STANDBY QUIESCENT CURRENT (<150A) INPUT TO OUTPUT SIGNAL TRANSFER FUNCTION PROGRAMMABLE LVS FUNCTION TTL AND CMOS COMPATIBLE INPUTS OUTPUT CURRENT LIMITATION CONTROLLED OUTPUT SLOPE FOR LOW EMI OVERTEMPERATURE SHUT-DOWN ABLE TO SURVIVE UNDER LOSS OF
SO24 ORDERING NUMBER: L5951
s
GROUND OR BATTERY ESD PROTECTED
DESCRIPTION The L5951 is a monolithic triple regulator integrated with a SAE J1850 Integrated Driver / Receiver realized in advanced Multipower-BCD technology. It is intended to drive single wire J1850 communications, and offer microcontroller power and power management for automotive or industrial applications.
BLOCK DIAGRAM
VBAT SUPPLY SELECTOR LVS 3V STANDBY REG1
BANDGAP REFERENCE
5V STANDBY
REG2
RESET EN SLEEP ENABLE/ PROTECTION LOGIC
RESET
7.8V
REG3
BUS DRIVER
BUS
TX
WAVESHAPING FILTER
4X LOOP 4XEN AND LOOPBACK
LOSS OF GND PROTECTION
LOAD
RX
DIGITAL OUTPUT DRIVER
GND
D99AU991
January 2001
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L5951
1 FUNCTIONAL DESCRIPTION
1.1 General Features The L5951 is an integrated circuit which provides a J1850 physical layer as well three voltage regulators. The L5951 was developed to provide the power and Class 2/IDR interface for a microcontroller. 1.2 REG1 Output Voltage The REG1 regulator output is equal to 3.3V. The 3.3V regulator is non low drop out and can handle currents up to 100mA with short citcuit limit of 280mA. 1.3 REG2 Output Voltage The REG2 regulator output is equal to 5V and can handle currents up to 100mA with short citcuit limit of 280mA. The output stage of the 5V regulator is low dropout. 1.4 REG3 Output Voltage The REG3 regulator output is equal to 7.8V and can handle currents up to 100mA with short citcuit limit of 280mA. The output stage of the 7.8V regulator is low dropout. REG3 regulator is controlled by the EN (enable) pin of the IC. REG3 can be turned on and off by toggling the EN pin. A logic "1" on the EN pin enables REG3, while a logic "0" on the EN pin disables REG3. The maximum voltage when REG3 is off must be less than 0.2V. Sleep* Input - The Class 2 transmitter can be turned on and turned off by the Sleep* pin. Once the voltage level is above 2VDC, the transmitter is enabled. If the Sleep* pin drops below 0.8VDC, and EN is "0" the transceiver goes into a low power mode. In low power mode, REG3 and the transceiver are disabled. The L5951 will still receive messages and send them to the microcontroller out of the RX pin.
* denotes active low
LVS input - Reg1 and Reg2 are supplied by Vbat pin. The device could then dissipate a lot of power, causing thermal shutdown at high voltage. For this reason a secondary low voltage supply (LVS) can be used to reduce power dissipation. Reset* Output - The L5951 has low voltage or no voltage circuitry that is a warning to the microcontroller. If REG2 drops 0.3VDC below its normal operating voltage, the Reset* pin will go to a logic "0". Between the voltage levels of 4.65VDC (min) and 5.10VDC (max) on REG2, a reset will occur. There is a hysterisis of 50mV on the Reset* pin.
* denotes active low
Low Input Voltage Operation - If battery voltage level drops below 7.0V, the outputs are to remain alive and ready for the return of normal voltage battery levels. The L5951 will be able to retrieve data off the BUS and send it to the micrprocessor when the supply voltage is as low as 4.9V. The regulators should stay the same voltage as the battery voltage down to 7.0V minus operating headroom for the 7.8V regulator. BUS VOH,min are not guaranteed over all conditions below VBAT = 9.0V. Waveshaping - Messages sent by the microcontroller to the transceiver are routed to a waveshaping circuit. The digital signal is rounded at the switching points in order to reduce EMI emissions. A second order function, I = C*dV/dt, is used to control the rise and fall times of the transmission. The rise and fall times are controlled by an external resistor Rext . The waveshaping circuit can be enabled and disabled by the 4X pin. A logic "1" will disable the waveshape circuit and a logic "0" will enable the waveshape circuit. In 4X mode, the speed of the BUS is increased by a factor of four. Any signal coming from the microcontroller and going to the BUS must be waveshaped. If loopback(LOOP) is enabled, the signal coming from the micro through the TX pin is routed to the RX pin back to the micro with or without it being waveshaped. A logic "1" enables loopback and a logic"0" disables loopback. Nodes - The transmitter provides a wave-shaped 0 to 7.7 VDC waveform on the BUS output. It also receives waveforms and transmits a digital level signal back to a logic IC. The transmitter can drive up to 32 remote transceivers. These remote nodes may be at ground potentials that are 2 VDC, with respect to the assembly. Under this condition, waveshaping will only be maintained during 3 of the 4 corners. The L5951 is a remote node on the Class 2/IDR Bus. Each remote transceiver has a 470 + 10% pF capacitor on its output for EMI suppression,
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as well as a 10.6 kW + 5% pull down resistor to ground. The main node has a 3,300 + 10% pF capacitor on its output for EMI suppression, as well as a 1.5 k + 5% pull down resistor to ground. With more than 26 nodes there is no primary node , all nodes will have the 470 10% pF capacitor and the 10.6k 5% pull down resistor. No matter how many remote nodes are on the Class 2/IDR Bus, the RC of the Class 2/IDR Bus is maintained at approximately 5ms. The minimum and maximum load on the Class 2/IDR Bus is given below :
Capacitance Minimum Nodes Maximum Nodes (3.33 * .9) + (.47 * .9) = 3.39 nF Resistance to Ground (1.5 * 1.05) || (10.6 * 1.05) = 1.38 k
(3.3 * 1.1) + 25*(0.47 * 1.1) = 16.55 nF (1.5 * 0.95) || (10.6 * 0.95) / 25 = 314
1.5 Protection The L5951 can survive under the following conditions: shorting the outputs to BAT and GND, loss of BAT, loss of IC GND, double battery(+26.5V), 4000V ESD, 34V load dump. L5951 will not handle a reverse battery condition. External components must be implemented for reverse battery protection. Thermal Shutdown: thermal shutdown is broken down into two areas; V1 and V2 ouputs, and the other is V3 output and the Class 2 Bus Driver. V1 and V2 outputs shutdown at 160C and returns to normal operation at 130C. The V3 output and Class 2 Bus Driver shutdown at 150C and return to normal operation at 120C. Current Limiting: each voltage regulator will contain its own current protection, and the maximum allowable current for all three regulators is 280mA. Short Circuit: If the outputs are short circuited, the IC will begin current limiting and eventually the thermal shutdown will kick in. Current limiting will not disable the outputs. Overvoltage: The IC will not operate if the BAT voltage reaches 30V or above. V1 and V2 will not be shutdown, but all other outputs will not operate. Loss of Ground & Loss of Battery Connection: in this conditions a very small leakage on BUS is generated. 1.6 Protocol Description The L5951 uses a Variable Pulse Width (VPW) modulated protocol. One frame consists of an entire message not containing more than 12 bytes. The first bit of each byte will be the most significant bit (MSB). A transmitted message begins with a SOF signal and ends with the EOF signal. The data to be transmitted has to be in a specific format as follows: idle,SOF,DATA, CRC, EOD, NB, IFR, EOF, IFS, idle Definitions below: idle: SOF: DATA: CRC: EOD: NB: IFR: EOF: IFS: BRK: Logic level low on communication bus Start of Frame Data Bytes Cyclic Redundancy Check Error Detection Byte End of DATA(only when IFR is used) Normalization Bit In-Frame Response Byte(s) End of Frame Inter-Frame Separation Break(can occur on network at any time)
Idle - Logic level low on bus any time after IFS. Start of Frame (SOF) - The SOF signals the receiver that a new frame is beginning. SOF signal is a logic level
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high pulse identified by a pulse width of about t = 200s. DATA - Total number of bytes that can be transmitted (from SOF to EOF) is 12 bytes. Cyclic Redundancy Check (CRC) - A method for determining if the message received is the same as the message transmitted. If an invalid CRC number is detected, then an error will be detected. The SOF signal is not used to determine the CRC. All bits in the CRC are initially "ones" to avoid confusion with a data stream that are all "zeros". End of Data (EOD) - Used to signal the receiver about the end of data transmission. If there is a IRF signal, the sender of the frame will expect one or more bytes in the IFR following the EOD. If there is no IFR used, then the bus would stay in a logic level low state resulting in a EOF. EOD signal is recognized by a logic level low pulse for a duration of about 200s. Normalization Bit (NB) - The sole reason for the NB is to define the start of the in-frame response. The first bit the the IFR is passive, therefore it is necessary to have a signal that follows EOD. There are two forms to the NB. First of all, the NB is a logic level high pulse. The two forms are distinguished by thier pulse widths. The first form has a pulse width of about 64s and indicates if the IFR contains a CRC or not. The second form has a longer pulse width of about 128s and also indicates if there is a CRC in the IFR or not. The manufacturer can manipulate the NB to any of the two methods. In-Frame Response (IFR) - Response bytes are sent by the receiver of the transmission and start after the EOD. If the IFR stays at a logic level low for a period of time then the frame must be considered to be complete. IFR bytes can be used to send a signal back to the originator indicating the correct CRC number to confirm the correct message was sent. End of Frame (EOF) - Indicates the end of a frame. Once the last byte is transmitted, the bus will be in a logic level low state for a period of time indicating the end of the frame. EOF signal is recognized by a low pulse for a width of about 280s. Inter-Frame Separation (IFS) - IFS is used to synchronize the receivers at various nodes. ABSOLUTE MAXIMUM RATINGS
Symbol VS VDIAG VIN VOUT VS Top Tstg Parameter DC Operating Supply Voltage Diagnostic output voltage Input Control Voltage (EN, Sleep, 4X, Loop, TX) Output Control Voltage (Reset *) Peak Supply Voltage t = 50ms Operating Temperature Range Storage Temperature Range
* denotes active low
Value -0.6 to 26.5 -0.6 to 5.5 -0.6 to 5.5 -0.3 to 5.5 34 -40 to 85 -40 to 150
Unit V V V V V C C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance junction to ambient (*) Value 50 Unit C/W
(*) With 6cm2 on board heat sink area.
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PIN CONNECTION
REG1 RESET REXT GND_REG GND_TX GND_TX GND_TX GND_TX SLEEP EN 4X LOOP 1 2 3 4 5 6 7 8 9 10 11 12
D99AU992
24 23 22 21 20 19 18 17 16 15 14 13
LVS REG2 REG3 BAT GND_TX GND_TX GND_TX GND_TX BUS LOAD TX RX
PIN FUNCTIONS
N. 1 2 3 4 ,6,7,8,17, 18,19,20 9 0 11 12 13 14 15 16 21 22 23 24 Name REG1 Reset * Rext GND_REG GND_TX Sleep * EN 4X LOOP RX TX Load Bus Bat REG3 REG2 LVS Regulator #1 Reset Output to C Waveshaping Resistor Regulator Ground Transceiver Ground Transceiver Enable Input Enable for Regulator #3 4XBus mode (41.6K Baud) Loopback Enable Serial Data Output to mC Serial Data Input from mC External Pull Down to Gnd Bus Output to Vehicle Battery Supply Regulator #3 Regulator #2 Low Voltage Supply Function
*denotes active low for Sleep and Reset.
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ELECTRICAL CHARACTERISTICS (Tamb = 25C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol Iq,ST-BY Parameter Standby Quiescent Current Test Condition EN, Sleep* = 0V, VBAT = 14V, IREG2 = 50mA, IREG1 = 50mA EN, Sleep* = 0V, VBAT = 14V, IREG2 = 500A, IREG1 = 250mA VBAT = 14V, IREG1 = 100mA, IREG2 = 100mA, IREG3 = 100mA, IBUS = 30mA LVS = 0V LVS = 10V VBAT = 14V, IREG1 = 100mA, IREG2 = 100mA, IREG3 = 100mA, IBUS = 30mA LVS = 10V VBAT = 14V, EN 2V VBAT = 14V, EN 0.8V VBAT = 14V, VIL VBAT = 14V, VIH Set VBATso VREG2 drops 0.30V Decrease VBATso VREG2 drops until Reset* drops 2 0 0.02 VREG2 - 0.20 50 0.4 V V mV Min. Typ. 350 110 Max. Unit A A
Maximum QuiescentCurrent VBAT
10 10.5
mA mA
Maximum QuiescentCurrent LVS
750 0 0 0.8
A A A V
EN Switch Input Current
VENL, ENH EN Input Threshold Voltage VRES, L VRES Reset* Output Low Voltage Reset* Output Voltage Threshold
VRES, HYS Reset Threshold Hysteresis
(*) Denotes active low.
3.3V/100mA DC Characteristics for Regulator Output 1
VREG1 Vline Output Voltage Line Regulation IREG1 =100mA 7V VBAT 26V (Measure VREG1 Across VBAT Range) 0.5mA IREG1 100mA (Measure VREG1 Across VLOAD Range) IREG1 = 100mA IREG1 = 5mA 3.14 3.3 7 3.46 15 V mV
Vload
Load Regulation
8
50
mV
VDROPOUT Dropout Voltage (Measure VBAT VREG1 when VREG1 drops 0.1V) Ilim1 SVR1 Current Limit Reg1 Supply Voltage Rejection
1 0.12 200
2.2 1.5
V V mA dB
IREG1 = IREG2 = IREG3 = 50mA f = 20 to 20kHz VBAT = 14Vdc, 1Vac,pp
45
5V/100mA Regulator Output 2 VREG2 Vline Output Voltage Line Regulation IREG2 =100mA 7V VBAT 26V (Measure VREG2 Across VBAT Range) 4.75 5 6 5.25 40 V mV
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ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol Vload Parameter Load Regulation Test Condition 0.5mA IREG2 100mA (Measure VREG2 Across VLOAD Range) IREG2 =100mA IREG2 =5mA Min. Typ. 14 Max. 100 Unit mV
VDROPOUT Dropout Voltage (Measure VBAT VREG2 when VREG2 drops 0.1V) Ilim2 SVR2 Current Limit Reg2 Supply Voltage Rejection
450 22 200
mV mV mA dB
IREG1 = IREG2 = IREG3 = 50mA f = 20 to 20kHz VBAT = 14Vdc, 1Vac,pp
45
7.8V/100mA Regulator Output 3 VREG3 DVline Output Voltage Line Regulation IREG3 =100mA - 8.8V VBAT Range 8.8V VBAT 26V (Measure VREG3 Across VBAT Range) 5mA IREG3 100mA (Measure VREG3 Across VLOAD Range) IREG3 = 100mA IREG3 = 5mA 0.5 0.04 7.60 7.8 8 50 V mV
DVload
Load Regulation
50
mV
VDROPOUT Dropout Voltage (Measure VBAT - VREG3 when VREG3 drops 0.1V) Ilim3 SVR3 Current Limit Reg3 Supply Voltage Rejection
V V
200 IREG1 = IREG2 = IREG3 = 50mA f = 20 to 20kHz VBAT = 14Vdc, 1Vac,pp 45
mA dB
DC Characteristics for Class 2 Transceiver Standard Loads: I REG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA BUSih BUSil BUSHyst BUSov BUS Guaranteed Input Voltages BUS Hysteresis BUS Output Voltage Verify RX > 3 VDC Verify RX < 3 VDC BUSItoh - BUShhtol TX = 5 VDC, BUS = 257 to 1380 to gnd VBAT - 8.2 to 16 VDC VBAT - 6.0 to 8.2 VDC TX = 0V TX = 5VDC BUS = -2 to 4.8VDC BUS = -2 to 0 VDC BUS = 0 to VBAT I LOAD = 6mA 4.25 3.7 3.50 0.15 V V V
7.2 5
V V
IBUSshort IBUSleak
BUS Short Circuit Current BUS Leakage Current
170 0 0 0.045
mA mA mA V
LOADON Load Output
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ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol Parameter Test Condition V BAT = 0V, ILOAD = 6mA IVBAT = 0mA, BUS = -18 to 9VDC LOAD = -18 to 0 VDC Verify BUS < 3.875VDC Verify BUS > 3.875VDC TX = 5VDC TX = 0VDC Normal Mode 4X Mode 4X = 5 VDC 4X = 0 VDC Normal Mode Loopback Mode LOOP = 5VDC LOOP = 0VDC BUS = 7V, IRX = -200A BUS = 0V, IRX = 1.6mA RX = high (Short circuit protection limits) TX = 5VDC Verify BUS > 3.725 Verify BUS < 4.025 Sleep* = 5VDC Sleep* = 0VDC 2 0.8 0.2 0 2 110 0 1.4 Min. Typ. 0.7 11 39 0.8 Max. Unit V A A V V A A V A A 0.8 2 0 V V A V V mA
LOADDio Load Output (Unpowered) IBUSloss BUS & LOADCurrent during loss ILOADloss of assembly VBAT or GND TXVIL TXVIH ITXVIL ITXVIH 4Trip1 4Trip2 I4Xvih I4Xvil LTrip1 LTrip2 ILvih ILvil VRXhigh VRXlow IRX TX Input Voltage
TX Input Current
4X Input Trip Point Voltages
4X Input Current
0 0
LOOP Input Trip Point Voltages
LOOP Input Current
RX Output Voltage, High RX Output Voltage, Low RX Output Current Sleep* Input Voltage
4.85 0.2 5
Sleep* VIH Sleep*VIL ISleepvih ISleepvil Sleep* Input Current
V V A A
* Denotes active low for Sleep and Reset.
AC Characteristics for Class 2 Transceiver Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA BUSLTOH BUS Voltage Rise Times TX = 7.812Hz square wave See Figure 1 Min and Max Loaded BUS TX = 7.812Hz square wave See Figure 1 Min and Max Loaded BUS TX = 7.812Hz square wave See Figure 2 Load BUS with 3.300pF and 1.38k Meas. @ 1.5V levels Meas. @ 6.25V levels
15
s
BUSHTOL BUS Voltage Fall Times
14
s
tWbus
BUS Pulse Width Distortion
77 48
s s
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ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol V1 V2 Parameter Spectral Content Limit (Measure spectral peak from 0.53MHz to 1.6MHz) Test Condition VBAT = 9V to 16V, no ground offset, 0.53 f 1MHz. VBAT = 9V to 16V, no ground offset, 1 f 1.67MHz. Measure Delay Between TX Trip Point and RX Trip Point Measure from 2.5V on TX to 3.875V on BUS 4X Mode Normal Mode See Figure 4 Measured from BUS Threshold Voltage Load RX with 50pF to Ground See Figure 5 Load RX with 50pF to Ground See Figure 5, Sleep* = 0VDC Min. Typ. 100 80 Max. Unit V V s
BUSDLY
Propagation Delay TX to BUS Delay
16
TX4XDLY TXNormDLY RXLTOHdly RX Output Delay Time RXHTOLdly RXLTOH RXHTOL RXLTOH RXHTOL RX Output Transition Time
3.5 14.5 1.5 1.9 170 70 170 70
s s s s ns ns ns ns
RX Output Transition Time During Sleep State
2
BUS TIMING DIAGRAM
Figure 1. BUS Rise and Fall Times
5V TX 0V 64sec
6.25V BUS 1.5V trise tfall
6.25V
1.5V
D99AU993
Figure 2. BUS Pulse Width Distortion
5V TX 0V 64sec
6.25V BUS 3.875V 1.5V
>35sec 64sec <93sec
D99AU994
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Figure 3. BUS Output Voltage
V
D99AU995
8
BUS 7
6
5
4 0 20 40 60 80 100 time(s)
Figure 4. BUS to RX Delay Times
tltoh 90% RX 10% 10% 90%
thtol
D99AU997
3
TYPICAL APPLICATION CURCUIT
Figure 5. Application Circui
BAT EN R1 47K LVS BUS/BUS OUT C9 R2 10.7K 470pF LOAD/BUS IN
VBATT EN C1 0.1F
C10 470F
10V C8 0.1F
REG1 REG2 5VSB 7.8VSW C7 10F REXT R3 68K GND
D99AU998mod
3.3VSB
SLEEP 4X FROM LOGIC LOOP TX RX TO LOGIC RESET
REG3
C5 10F
C3 10F
Note: ESR of output capacitors should be between 0.2 and 5.0.
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L5951
4 TYPICAL RESET CIRCUIT
Figure 6. Reset Circuit
5VSB R RESET
to micro C
D99AU999
1) 10k is the minimum resistance for R. 2) The value of C depends on timing needed
External Components Parts List for Standard Application
Quantity 5 3 1 1 1 1 1 Application Description C1, C8 C3, C5, C7 R1 R2 R3 C9 C10 Part Description CAP - 0.1F, 25V CAP - Tant 10F, 10V RES-47k, 1/16W 5% RES - 10.7k, 1/16W, 1% RES - 68k, 1/16W, 1% CAP - 25V, 470pF CAP - 50V, 470pF Note Number 1 2 3 4 5 6 1
Notes: (Reasons for This Component Choice) 1. Noise Suppression 2. Output Compensation 3. Pull Down Resistor 4. Bus Resistor 5. Bus Slew Rate Control 6. Proper Bus Capacitance
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DIM. MIN. A A1 A2 B C D E e H h k L 0.40 10.0 0.25 0.33 0.23 15.20 7.40 2.35 0.10
mm TYP. MAX. 2.65 0.30 2.55 0.51 0.32 15.60 7.60 1.27 10.65 0.75 0.394 0.010 0.013 0.009 0.598 0.291 MIN. 0.093 0.004
inch TYP. MAX. 0.104 0.012 0.100 0.0200 0.013 0.614 0.299 0,050 0.419 0.030
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.)
SO24
1.27 0.016 0.050
h x 45
A2
A1
A
0.10mm .004 Seating Plane
B
e
K L H
A1
C
D
24
13
1
12
SO24
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E
L5951
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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